By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The awareness of sign sampling and quantization at excessive pattern premiums with low strength dissipation is a crucial target in lots of functions, includ ing transportable video units akin to camcorders, own verbal exchange units corresponding to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic info detection, etc. This paper describes structure and circuit methods for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive velocity is taken to indicate sampling premiums above 1 Mhz. within the first part the dif ferent conversion options appropriate during this variety of pattern charges is dis stubborn. Following that the actual difficulties linked to strength minimization in video-rate pipeline ADCs is mentioned. those comprise optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal energy dissipation. for instance of the appliance of those tech niques, the layout of a power-optimized lO-bit pipeline relief converter (ADC) that achieves =1. sixty seven mW in step with MS/s of sampling cost from 1 MS/s to twenty MS/s is defined. 2. strategies for CMOS Video-Rate reduction Conversion Analog-to-digital conversion strategies might be classified in lots of methods. One handy technique of evaluating recommendations is to ascertain the variety of "analog clock cycles" required to provide one powerful output pattern of the sign being quantized.
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Additional info for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
The result from doing the analysis this way is the same as the result above. Thus, minimizing power for fixed speed is equivalent to maximizing speed for fixed power. 8 micron, and power supply voltage of 3 volts, effective channel mobility of about 500cm2N-sec, and optimum time constant of 400ps, the power dissipation of the optimum gain block is approximately lOmW assuming a telescopic operational amplifier. A time constant of 400ps would allow a settling time on the order of 5ns, and a clocking rate of 50 to 100Msamples/sec.
Cascoded CMOS rail-to-rail output stage with feedback-biased class-AB control. v ss BiCMOS offers new possibilities for low-voltage low-power design. The large current-gain of MOS transistors can be combined with the large gm of bipolar transistors. An example is shown in Fig. 37, the CMOS transistor, Mj> tremendously boosts the current gain of the bipolar output transistor, Qj. The high frequency behavior of this circuit is even worse as the Darlington stage, as shown Fig. 32. The minimum supply voltage is also larger than the Darlington stage.
12. Rail-to-rail CMOS complementary input stage. If the N-channel and P-channel input pair are placed in parallel, as is shown in Fig. 12, the common-mode input voltage range becomes: (14) To obtain a rail-to-rail operation of the complementary input stage the supply-voltage should have a minimum value of: Vsup,min = 2VGS + 2VDsat (15) If the supply voltage is below this value a gap occurs in the common-mode input range. 8 V. Of course, this voltage depends on the bias-current level and the threshold voltage of the transistors.